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password access security supervisor xicor, inc. 1994, 1995, 1996 patents pending 7002-2.1 1/19/96 t0/c0/d19 ns 1 characteristics subject to change without notice 4k X76F041 4 x 128 x 8 bit pass tm secureflash features 64-bit password security three password modes secure read access secure write access secure con?uration access programmable con?uration read, write and con?uration access passwords multiple array access/functionality retry register/counter 8 byte sector write (4) 1k memory arrays iso response to reset low power cmos ?0 m a standby current 3ma active current two voltage ranges 3v to 3.6v 5v 10% high reliability endurance: 100,000 cycles data retention: 100 years esd protection: 2000v on all pins description the X76F041 is a password access security supervisor device, containing four 128 x 8 bit secureflash arrays. access can be controlled by three 64-bit programmable passwords, one for read operations, one for write opera- tions and one for device con?uration. the X76F041 features a serial interface and software protocol allowing operation on a simple two wire bus. the bus signals are a clock input (scl) and a bidirec- tional data input and output (sda). access to the device is controlled through a chip select input (cs ), allowing any number of devices to share the same bus. the X76F041 also features a synchronous response to reset; providing an automatic output of a pre-con?ured 32-bit data stream conforming to the iso standard for memory cards. the X76F041 utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. functional diagram interface logic chip enable (4) 16 x 64 secureflash arrays 180?ff 100?7f 080?ff 000?7f sda scl rst cs 7002 ill f01 data transfer array access enable password array and password verification logic iso reset response data register configuration register retry counter thi d t t d ith f m k 4 0 2
X76F041 2 pin description serial data input/output (sda) sda is a true three state serial data input/output pin. during a read cycle, data is shifted out on this pin. during a write cycle, data is shifted in on this pin. in all other cases this pin is in a high impedance state. serial clock (scl) the serial clock controls the serial bus timing for data input and output. chip select (cs ) when cs is high, the X76F041 is deselected and the sda pin is at high impedance and unless an internal write operation is underway the X76F041 will be in the standby power mode. cs low enables the X76F041, placing it in the active power mode. reset (rst) rst is a device reset pin. when rst is pulsed high while cs is low the X76F041 will output 32 bits of ?ed data which conforms to the iso standard for ?ynchronous response to reset? cs must remain low and the part must not be in a write cycle for the response to reset to occur. if at any time during the response to reset cs goes high, the response to reset will be aborted and the part will return to the standby mode. pin configuration 7002 frm t01 symbol description cs chip select input sda serial data input/output rst reset input scl serial clock input v ss ground v cc supply voltage nc no connect 7002 ill f02 v cc rst scl nc 1 2 3 4 8 7 6 5 v ss cs sda nc X76F041 dip/soic
X76F041 3 device operation there are three primary modes of operation for the X76F041; read, write and configuration. the read and write modes may be performed with or without an 8-byte password. the configuration mode always requires an 8-byte password. the basic method of communication is established by ?st enabling the device (cs low), generating a start condition and then transmitting a command and address ?ld followed by the correct password (if con?ured to require a password). all parts will be shipped from the factory in the non-password mode. the user must per- form an ack polling routine to determine the validity of the password and start the data transfer (see acknowl- edge polling). only after the correct password is accepted and an ack polling has been performed can the data transfer occur. to ensure correct communication, rst must remain low under all conditions except when initiating a ?esponse to reset sequence? figure 1. X76F041 device operation load low order address / configuration instruction byte load 8?yte password (if applicable) verify password acceptance by use of ack polling (if applicable) read / write data bytes load command+high order address byte 7002 ill f03 data is transferred in 8-bit segments, with each transfer being followed by an ack, generated by the receiving device. if the X76F041 is in a nonvolatile write cycle a ?o ack (sda high) response will be issued in response to load- ing of the command + high order address byte. if a stop condition is issued prior to the nonvolatile write cycle the write operation will be terminated and the part will reset and enter into a standby mode. the basic sequence is illustrated in figure 1. after each transaction is completed, the X76F041 will reset and enter into a standby mode. this will also be the response if an attempt is made to access any limited array. password registers the three passwords, read, write and con?uration are stored in three 64 bit write only registers as illus- trated in ?ure 2. figure 2. password registers device configuration five 8-bit con?uration registers are used to con?ure the X76F041. these are shown in ?ure 3. figure 3. configuration registers 64 bit write password 64 bit read password 64 bit configuration password 63 0 7002 ill f04 acr1 acr2 cr rr rc res res res reserved retry register configuration register array control register 2 array control register 1 retry counter 7002 ill f04b 63 0
X76F041 4 array control the four 1k arrays, are each programmable to different levels of access and functionality. each array can be pro- grammed to require or not require the read/write pass- words. the functional options are: read and write access. read access with all write operations locked out. read access and program only (writing a ??to a ??. if an attempt to change a ??to a ??occurs the X76F041 will reset, issue a ?o ack?and enter the standby power mode. no read or write access to the memory. access only through use of the con?uration password. array map 8 bit array control register 1 8 bit array control register 2 functional bits 7002 frm t02 z t functionality 0 0 read and write unlimited 1 0 read only, write limited 01 program & read only, erase limited 11 no read or write, fully limited addresses 000 07f (hex) addresses 080 0ff (hex) addresses 100 17f (hex) addresses 180 1ff (hex) first ?k second ?k third ?k fourth ?k high-order addresses 7002 ill f04a x2 y2 z2 t2 x1 y1 z1 t1 second 1k first 1k access function access function msb lsb 7002 ill f05a x4 y4 z4 t4 x3 y3 z3 t3 upper 1k third 1k access function access function msb lsb 7002 ill f05b access bits 7002 frm t03 8-bit configuration register unauthorized access bits (ua1, ua2): 1 0 access is forbidden if retry register equals the retry counter (provided that the retry counter is enabled) and no further access of any kind will be allowed. 0 1, 0 0, 1 1 only con?uration operations are allowed if the retry reg- ister equals the retry counter (provided that the retry counter is enabled). retry counter reset bit (rcr): if the retry counter reset bit is a ??then the retry counter will be reset following a correct password, provided the retry counter is enabled. if the retry counter reset bit is a ??then the retry counter will not be reset following a correct password, provided the retry counter is enabled. retry counter enable bit (rce): if the retry counter enable bit is a ?? then the retry counter is enabled. an initial comparison between the retry register and retry counter determines whether the number of allowed incorrect password attempts has been reached. if not, the protocol continues and in case of a wrong password, the retry counter is incremented by one. if the password is correct then the retry counter will either be reset or unchanged, depending on the reset bit. xy read password write password 0 0 not required not required 1 0 not required required 0 1 required not required 1 1 required required ua1 ua2 1 0 rcr rce 0 0 reserved retry counter reset reserved reserved unauthorized access bit 2 retry counter enable unauthorized access bit 1 msb lsb 7002 ill f06
X76F041 5 the retry register must have a higher value than the retry counter for correct device operation. if the retry counter value is larger than the retry register and the retry counter is enabled, the device will wrap around allowing up to an additional 255 incorrect access attempts. if the retry counter enable bit is a ?? then the retry counter is disabled. retry register/counter both the retry register and retry counter are accessible in the con?uration mode and may be programmed with a value of 0 to 255. the difference between the retry register and the retry counter is the number of access attempts allowed, there- fore the retry counter must be programmed to a smaller value than the retry register to prevent wrap around. device protocol the X76F041 supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers, and provide the clock for both transmit and receive operations. therefore, the X76F041 will be considered a slave in all applications. start condition all commands except for response to reset are preceded by the start condition, which is a high to low transition of sda when scl is high. the X76F041 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. figure 4. data validity during write figure 5. definition of start and stop note: the part requires the scl input to be low during non-active periods of operation. in other words, the scl will need to be low prior to any start condition and low after a stop condition. this is also re?cted in the timing diagram. scl sda data stable data change 7002 ill f07 scl sda start bit stop bit 7002 ill f08
X76F041 6 stop condition all communications must be terminated by a stop condi- tion, which is a low to high transition of sda when scl is high. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. operational modes 7002 frm t04 the first byte in the protocol the second byte in the protocol command description password used: 0 0 0xxxxa write address write (sector) write 0 0 1xxxxa read address read (random / sequential) read 0 1 0xxxxa write address write (sector) configuration 0 1 1xxxxa read address read (random / sequential) configuration 1 0 0xxxxx 0 0 0 0 0 0 0 0 program write-password write 1 0 0xxxxx 0 0 0 1 0 0 0 0 program read-password read 1 0 0xxxxx 0 0 1 0 0 0 0 0 program configuration-password configuration 1 0 0xxxxx 0 0 1 1 0 0 0 0 reset write password (all 0?) configuration 1 0 0xxxxx 0 1 0 0 0 0 0 0 reset read password (all 0?) configuration 1 0 0xxxxx 0 1 0 1 0 0 0 0 program configuration registers configuration 1 0 0xxxxx 0 1 1 0 0 0 0 0 read configuration registers configuration 1 0 0xxxxx 0 1 1 1 0 0 0 0 mass program configuration 1 0 0xxxxx 1 0 0 0 0 0 0 0 mass erase configuration all the rest reserved
X76F041 7 write operation sector write the sector write mode requires issuing the 3-bit write command followed by the address, password if required and then the data bytes transferred as illustrated in fig- ure 6. eight bytes must be transferred. after the last byte to be transferred is acknowledged, a stop condition is issued, which starts the nonvolatile write cycle. if more than 8 bytes are transferred the data will wrap around and previous data will be overwritten. all data will be writ- ten to the same sector as de?ed by a 8 ? 3 . figure 6. sector write s t a r t s cmda x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k write password 7 a c k a c k a c k a c k write password 0 wait t wc /ack polling data 0 a c k a c k s t o p sda line if password match then s data 7 wait t wc data 1 data 2 a c k a c k a c k 7002 ill f10.1
X76F041 8 ack polling once a stop condition is issued to indicate the end of the hosts write sequence, the X76F041 initiates the internal nonvolatile write cycle. in order to take advantage of the typical 5ms write cycle, ack polling can be initiated immediately. this involves issuing the start condition fol- lowed by the new command code of eight bits (1st byte of the protocol). if the X76F041 is still busy with the nonvol- atile write operation, it will issue a ?o ack?in response. if the nonvolatile write operation has completed, an ?ck?will be returned and the host can then proceed with the rest of the protocol. refer to the following ?w: ack polling sequence 7002 ill f12a write sequence completed enter ack polling issue a start issue new command code (1st byte) ack returned proceed no ack (sda high) yes (sda low) after a password sequence, there is always a nonvolatile write cycle. in order to continue the transaction, the X76F041 requires the master to perform an ack polling with the speci? code of c0h. as with regular acknowl- edge polling the user can either time out for 10ms, and then issue the ack polling once, or continuously loop as described in the ?w. as with regular acknowledge polling, if the user chooses to loop, then as long as the nonvolatile write cycle is active, a no ack will be issued in response to each poll- ing cycle. if the password that was inserted was correct, then an ?ck?will be returned once the nonvolatile write cycle is over, in response to the ack polling cycle immediately following it. if the password that was inserted was incorrect, then a ?o ack?will be returned even if the nonvolatile write cycle is over. therefore, the user cannot be certain that the password is incorrect until the 10ms write cycle time has elapsed. figure 7. acknowledge polling scl sda 8th clk. of 8th pwd. byte ?ck clk 8th clk ack clk 8th bit ?ck ack or no ack start condition 7002 ill f11
X76F041 9 read operation random read with password random read with password operations are initiated with a start command followed by the read command and the address of the ?st byte of the block in which data is to be read: block 0 = 000h block 1 = 080h block 2 = 100h block 3 = 180h this is followed by the eight byte read password sequence which includes the 10ms wait time and the password acknowledge polling sequence. if the pass- word is accepted an ?ck?will be returned followed by eight bits of ?ecure read setup?which is to be ignored. at this point a start is issued followed by the address and data to be read within the original 1k block. see ?ure 8. once the ?st byte has been read, another start can be issued followed by a new 8-bit address. random reads are allowed only within the original 1k-bit block. to access another 1k-bit block, a stop must be issued fol- lowed by a new command/block address/password sequence. figure 8. random read with password s t a r t s cmda x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k read password 7 a c k a c k a c k a c k read password 0 secure read setup a c k s t a r t sda line if password match then data 0 a c k s t a r t ss 7002 ill f13.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 wait t wc /ack polling a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 1 a c k s t o p s first byte block address xxxxxxxx
X76F041 10 random read without password random read operations without a password do not require the ?st byte block initiation address. to perform a random read without password, a start is followed by the read command plus address location of the byte to be read. this is followed by an ?ck?and the eight bits of data to be read. other bytes within the same 1k-bit block may be read by issuing another start followed by a new 8-bit address as shown in ?ure 9. sequential read once past the password acceptance sequence (when required) and ?ecure read setup? the host can read sequentially within the originally addressed 1k-bit array. the data output is sequential, with the data from address n followed by the data from address n+1. the address counter for read operations increments the address, allowing the 1k memory contents to be serially read dur- ing one operation. at the end of the address space (address 127), the counter ?olls over?to address space 0 within the 1k block and the X76F041 continues to out- put data for each acknowledge received. refer to ?ure 10 for the address, acknowledge and data transfer sequence. an acknowledge must follow each 8-bit data transfer. after the last bit has been read, a stop condition is generated without a preceding acknowledge. figure 9. random read without password figure 10. sequential read with password s t a r t s cmda x a x a x a x a 8 a c k a c k sda line a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 0 s t a r t s 7002 ill f13a.2 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 1 a c k s t o p s s t a r t s cmda x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k read password 7 a c k a c k a c k a c k read password 0 wait t wc /ack polling secure read setup a c k s t a r t s t o p sda line if password match then s data x data 0 a c k a c k 7002 ill f12.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 data 1 s xxxxxxxx first byte block address
X76F041 11 configuration operations con?uration commands generally require the con?u- ration password. the exception is that programming a new read/write password requires the old read/write password and not the con?uration password. in most cases these operations will be performed by the equip- ment manufacturer or end distributor of the equipment or card. configuration read/write con?uration read/write allows access to all of the non- volatile memory arrays regardless of the contents of the con?uration registers. access includes sector writes, random and sequential reads using the same format as normal reads and writes. in general, the con?uration read/write operation enables access to any memory location that may otherwise be limited. the con?uration password, in this sense, is like a master key that can override the limits caused by the control partitioning of the arrays. figure 11. configuration write figure 12. configuration sequential read s t a r t s cmda x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling data 0 a c k a c k s t o p sda line if password match then s data x wait t wc data 1 data 2 a c k a c k 7002 ill f14.1 a c k s t a r t s cmda x a x a x a x a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling secure read setup a c k s t a r t s t o p sda line if password match then s data x data 0 a c k a c k 7002 ill f15.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s data 1 first byte block address xxxxxxxx
X76F041 12 configuration of passwords the sequence in ?ure 14 will change (program) the write, read and con?uration passwords. the program- ming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password is consistent. after the eight bytes are entered in the sec- ond pass, a comparison takes place. a mismatch will cause the part to reset and enter into the standby mode and a ?o ack?will be issued. there is no way to read the read/write/con?uration passwords. program configuration registers this mode allows programming of the ?e con?uration/ control registers using the con?uration password. the retry counter must be programmed with a value less than the retry register. if it is programmed with a value larger than the retry register there will be a wrap around. read configuration registers this mode allows reading of the 5 con?uration/control registers with the con?uration password. it may be use- ful for monitoring purposes. figure 13. configuration random read figure 14. program passwords s t a r t s cmda x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling secure read setup a c k s t a r t sda line if password match then s a c k 7002 ill f16.3 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 first byte block address data 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s t a r t s a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a c k data 1 s t o p s xxxxxxxx s t a r t s cmda x a x a x a x a 8 a c k old password 7 a c k a c k a c k old password 0 wait t wc /ack polling new password 7 a c k a c k sda line if password match then new password 7 new password 0 a c k a c k read/write/ configuration instruction s t o p s new password 0 wait t wc a c k a c k 7002 ill f17.1
X76F041 13 read password reset this mode allows resetting of the read password to all ?? in case re-programming is needed and the old pass- word is not known. write password reset this mode allows resetting of the write password to all ?? in case re-programming is needed and the old pass- word is not known. mass program this mode allows mass programming of the array, con- ?uration registers and password to all ?? using a special con?uration command. all parts are shipped mass programmed. mass erase this mode allows mass erase of the array, con?uration register and password to all ?? using a special con?u- ration command. figure 15. program configuration registers figure 16. read configuration registers s t a r t s cmda x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling bcr 1 byte a c k a c k s t o p sda line if password match then s bcr 2 byte cr byte a c k a c k configuration instruction rc byte a c k a c k wait t wc rr byte 7002 ill f18.1 s t a r t s cmda x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc /ack polling bcr 1 byte a c k a c k s t o p sda line if password match then s bcr 2 byte cr byte a c k a c k rc byte a c k rr byte 7002 ill f19.1 configuration instruction
X76F041 14 absolute maximum ratings* temperature under bias ..................... ?5 c to +135 c storage temperature .......................... ?5 c to +150 c voltage on any pin with respect to v ss ..................................... ?v to +7v d.c. output current................................................. 5ma lead temperature (soldering, 10 seconds) .................................300 c *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. figure 17. read/write password reset figure 18. mass program/erase symbol table s t a r t s cmda x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc sda line configuration instruction s s t o p 7002 ill f20.1 wait t wc /ack polling s t a r t s cmda x a x a x a x a 8 a c k configuration password 7 a c k a c k a c k a c k configuration password 0 wait t wc sda line configuration instruction s s t o p 7002 ill f20a.1 wait t wc /ack polling waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
X76F041 15 recommended operating conditions 7002 frm t05 temp min. max. commercial 0 c +70 c extended ?0 c +85 c 7002 frm t06.1 supply voltage limits X76F041 4.5v to 5.5v X76F041 ?3 3v to 3.6v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) 7002 frm t07.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v 7002 frm t08 notes: (1) must perform a stop command after a read command prior to measurement (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 2ma f scl = v cc x 0.1/v cc x 0.9 levels @ 1mhz, sda = open rst = cs = v ss i cc2 (3) v cc supply current (write) 3ma f scl = v cc x 0.1/v cc x 0.9 levels @ 1mhz, sda = open rst = cs = v ss i sb1 (1) v cc supply current (standby) 100 m a scl = v ss , cs = v cc ?0.3v sda = open, rst = v cc = 5.5v i sb2 (1) v cc supply current (standby) 50 m a scl = v ss , cs = v cc ?0.3v sda = open, rst = v ss , v cc = 3v i li input leakage current 10 m a v in = v ss to v cc i lo output leakage current 10 m a v out = v ss to v cc v il1 (2) input low voltage ?.5 v cc x 0.3 v v cc = 5.5v v ih1 (2) input high voltage v cc x 0.7 v cc + 0.5 v v cc = 5.5v v il2 (2) input low voltage ?.5 v cc x 0.1 v v cc = 3.0v v ih2 (2) input high voltage v cc x 0.9 v cc + 0.5 v v cc = 3.0v v ol output low voltage 0.4 v i ol = 2ma v oh output high voltage v cc ?0.8 v i oh = ?ma symbol test max. units conditions c out (3) output capacitance (sda) 10 pf v i/o = 0v c in (3) input capacitance (rst, scl, cs )10 pf v in = 0v equivalent a.c. load circuit 3v 1.3k w output 100pf 7002 ill f21.1 5v 2.3k w output 100pf a.c. test conditions 7002 frm t09 input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf
X76F041 16 a.c. characteristics (over recommended operating conditions, unless otherwise specified) read & write cycle limits 7002 frm t10 notes: (4) this parameter is periodically sampled and not 100% tested. symbol parameter min. max. units f scl scl clock frequency 1 mhz ti noise suppression time constant at scl & sda inputs 20 ns t dv scl high to sda data valid 450 ns t low clock low period 500 ns t high clock high period 500 ns t stas1 start condition setup time to rising edge of scl 150 ns t stas2 start condition setup time to falling edge of scl 150 ns t stah1 start condition hold time to rising edge of scl 50 ns t stah2 start condition hold time to falling edge of scl 50 ns t stps1 stop condition setup time to rising edge of scl 150 ns t stps2 stop condition setup time to falling edge of scl 150 ns t stph1 stop condition hold time to rising edge of scl 50 ns t stph2 stop condition hold time to falling edge of scl 50 ns t hd:dat data in hold time 10 ns t su:dat data in setup time 150 ns t rscl (4) scl rise time 90 ns t fscl (4) scl fall time 90 ns t r (4) sda, cs , rst rise time 90 ns t f (4) sda, cs , rst fall time 90 ns t dh data out hold time 0 ns t hz1 scl low to high impedance 150 ns t lz scl high to output active 0 ns t vccs v cc to cs setup time 5ms t su:cs cs setup time 200 ns t hd:cs cs hold time 100 ns t hz2 cs deselect time 150 ns t su:scl scl setup time to cs low after power up 200 ns t rst rst high time 1500 ns t su:rst rst setup time 500 ns f scl:rst scl frequency during response to reset 1 mhz t low:rst scl low time during response to reset 500 ns t high:rst scl high time during response to reset 500 ns t pd scl low to sda valid during response to reset 450 ns t nol rst to scl non-overlap 500 ns t wc nonvolatile write cycle 10 ms
X76F041 17 bus timing (1) ?sda driven by the bus master bus timing (2) ?sda driven by the slave start condition timing notes: (1) the master may issue a stop condition at any given time in which it is driving the sda line. in other words, when the part is sending ack or data the master may not issue a stop condition. the part will not respond to any such attempt which also causes bus con- tention. at any other time, a stop condition will cause the part to reset and stop (enter a stand-by mode). write operations will termi- nate prior to entering the stand-by mode. (2) when the part drives the sda line, it will tri-state the bus only after the last bit of the sequence. in other words, after the 8th bit of a byte that is read or after ack between incoming bytes. in all other cases when the part drives the bus (between successive bits) it will con- tinue to drive the bus also during the clock low periods. scl sda (in) from master t fscl t rscl t low t high t su:dat t hd:dat t f t r start bit 7002 ill f22 1st clock pulse of sequence t dh t dv t lz t hz1 7002 ill f23 last clock pulse of sequence scl sda (out) from slave scl t stas1 t stah1 t stas2 t stah2 start bit 7002 ill f24 sda (in) from master
X76F041 18 stop condition timing acknowledge response from slave (same timing as data out) acknowledge response from master cs timing diagram (selecting/deselecting the part) scl t stps1 t stph1 t stps2 t stph2 stop bit 7002 ill f25 sda (in) from master scl sda (out) from slave (acknowledge) t lz t dv t dh t hz1 7002 ill f26 scl sda (out) from master (acknowledge) t su:dat t hd:dat 7002 ill f27 scl t su:cs t hd:cs cs from master 7002 ill f28
X76F041 19 v cc to cs setup timing diagram cs deselect rst timing diagram ?response to a synchronous reset (iso) notes: (1) the reset operation results in an answer from the part containing a header transmitted from the part to the master. the header has a ?ed length of 32 bits and begins with two mandatory ?lds of eight bits : h1 and h2. (2) the chronological order of transmission of the information bits shall correspond to bit identi?ation b1 to b32 with the least signi?ant bit transmitted ?st. (3) the current values are: h1 : 19 h h2 : 55 h h3 : aa h h4 : 55 h vcc cs t su:scl v ccmin t su:cs scl t vccs 7002 ill f29 cs sda (out) from slave t hz2 7002 ill f29a scl sda t nol t pd (low) 1st data bit 2nd data bit cs rst t rst 1st clk. pulse 2nd clk. pulse 3rd clk. pulse t su:rst t high_rst f scl_rst t low_rst t pd 7002 ill f30
X76F041 20 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (.508) 0.012 (.305) .080 (2.03) .070 (1.78) .213 (5.41) .205 (5.21) 0 8 .330 (8.38) .300 (7.62) .212 (5.38) .203 (5.16) .035 (.889) .020 (.508) .010 (.254) .007 (.178) ref pin 1 id .050 (1.27) bsc 8-lead plastic, 0.200?wide small outline gullwing package type ??(eiaj soic) .013 (.330) .004 (.102) 3926 ill f33.1 3926 fhd f01 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
X76F041 21 X76F041 x x ? ordering information v cc limits blank = 5v 10% 3 = 3v to 3.6v temperature range blank = commercial = 0 c to +70 c e = extended = ?0 c to +85 c package p = 8-lead plastic dip a = 8-lead soic (eiaj) h = die in waffle packs w = die in wafer form device limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue production and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detec- tion and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
u.s. sales offices corporate office xicor inc. 1511 buckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne @smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se @smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma @smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc @smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc @smtpgate.xicor.com international sales offices singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka @smtpgate.xicor.com ( ) = country code europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk @smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm @smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp @smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com xicor, inc., marketing dept. 1511 buckeye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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